A non-invasive, high-efficient and low-cost fault attack is realized on FPGA-based cryptographic applications. Based on the setup failures in critical paths, faults are injected into the FPGA devices by lowering the supply voltage. Then the encryption key can be retrieved efficiently with an appropriate fault model. In the attack experiments, the full 128-bit key of AES is retrieved correctly with only 8 pairs of correct and faulty ciphertexts within a few minutes, by using a power supply and a personal computer, based on the FPGA platform.

The authors propose a novel countermeasure which associates masking with RDI (random delay in- sertion). Further, multi-masking instead of transformed masking is proposed in order to defend DPA (differential power analysis) attack based on Hamming distance model. The combined countermeasure is implemented on Data Encryption Standard. The results show that combined countermeasure can defend DPA attack with 10⁵ power traces, and increase 40% ability against DPA attack.

Radio frequency identification (RFID) suffers extremely limited chip area and energy resource. A novel elliptic curve cryptographic (ECC) processer based on generalized binary Hessian curve (GBHC) is designed and implemented. The authors employ Montgomery Ladder scalar-multiplication algorithm and optimized w-coordinate method for accelerating the computing timing, and well-design circular shift register (CSR) architecture and clock gating technology for reducing the consumption of area and energy. The results show that the proposed processer has fast computing speed, minimal chip area and ultra-low energy consumption, and is capable to resist some types of side channel attack (SCA) such as simple power analysis (SPA).

The authors studied the DPA attack method and circuit level protection technology, and introduced a security circuit WDDL on FPGA and a new symmetrical routing technology. A 4-bit WDDL adder on FPGA (field programmable gate array) platform was implemented and the power consumption of the circuit was analyzed. The results show that power consumption of WDDL decreases obviously than that of the traditional circuit and WDDL circuit can reduce the correlation of power consumption and data effectively. WDDL is proved to have better anti DPA (differential power analysis) attack ability at the cost of chip size.

To study the vulnerability of Advanced Encryption Standard (AES) against electromagnetic side channel attacks, based on the method of correlation electromagnetic analysis (CEMA) attack, the authors built a platform to acquire EM emanation and process data, then performed a near-field CEMA attack against an FPGA implementation of AES-128. The results indicate that the platform is able to acquire the EM emanation of the encryption chip, and can retrieve all the 16 bytes of the 10th roundkey of AES. After the optimization of processing data, the efficiency of CEMA is highly enhanced, namely the data needed to exploit the correct roundkey is greatly reduced.

The authors discuss the performance and area of different large-scale Booth multipliers with high radices used in Montgomery algorithm using secondary encoded scheme. The modular multiplication is implemented with SMIC 0.13μm technology at the frequency of 160 MHz and 125 MHz respectively based on the 128-bit multiplier and 256-bit multiplier with Booth 64, 128 and 256 encoding. Experiment result shows that the multiplier with Booth 64, 128 and 256 can achieve the same timing performance, while the area rises as radix rises due to the complexity in pre-computation and partial product generation.

A dynamic reconfigurable digital system is proposed. By defining modulation and demodulation as reconfigurable modules, the proposed modem changes its modulation scheme and data rate according to underwater channel estimation results to provide low bit error rate and low energy consumption communication. The digital system is implemented on Xilinx XUPV5 FPGA board. Hardware and software co-verification show that the digital system works correctly and can be reconfigured to 2FSK and 2PSK mode. Compared to traditional FPGA development approach, dynamic reconfigurable design method improves flexibility of algorithm design and saves resource utilization of the digital system.

Based on the classical system design flow, a custom digital down converter (DDC) was designed and implemented for Homenet wireless communication system. At the system level, the behavior model of DDC was constructed with the assistant of system modeling tool MATLAB. At the circuit level, considering implementation complexity, a large number of digital filter optimizing schemes such as CSD and RAG were adopted; in our design, numerically controlled oscillators (NCO) was based on a new hybrid scheme, which combines the respective advantages of LUT and CORDIC algorithm. Homenet system verification flat including our custom digital down converter was implemented with Xilinx VirtexII XC2V1000-4FG256 FPGA.